arch/mips/ath79/setup.c

215

set_io_port_base(KSEG1);

arch/mips/econet/init.c

43

set_io_port_base(KSEG1);

arch/mips/include/asm/addrspace.h

86

#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)

arch/mips/include/asm/addrspace.h

94

#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)

arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h

34

#define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))

arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h

35

#define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))

arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h

36

#define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))

arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h

94

#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)

arch/mips/lantiq/falcon/prom.c

34

#define BOOT_REG_BASE (KSEG1 | 0x1F200000)

arch/mips/lantiq/falcon/reset.c

25

#define BOOT_REG_BASE (KSEG1 | 0x1F200000)

arch/mips/lantiq/falcon/reset.c

31

#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)

arch/mips/lantiq/prom.c

76

set_io_port_base((unsigned long) KSEG1);

arch/mips/ralink/of.c

91

set_io_port_base(KSEG1);

arch/mips/rb532/setup.c

50

set_io_port_base(KSEG1);

arch/mips/txx9/rbtx4927/setup.c

224

set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);