arch/sh/kernel/cpu/sh4a/setup-sh7343.c

364

INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

388

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

410

{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

577

INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

602

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

624

{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

1030

JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

1060

{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

988

INTC_VECT(JPU, 0x560),