JH7110_SYSCLK_DDR_BUS
JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 0, 4,