J721E_CLK_PARENT_48000
if (!(rate % 8000) && priv->pll_rates[J721E_CLK_PARENT_48000])
clk_id = J721E_CLK_PARENT_48000;
else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_48000])
clk_id = J721E_CLK_PARENT_48000;
clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15",
clocks->parent[J721E_CLK_PARENT_48000] = parent;
!clocks->parent[J721E_CLK_PARENT_48000]) {
[J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
[J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
[J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */
pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_48000]);
priv->pll_rates[J721E_CLK_PARENT_48000] =
match_data->pll_rates[J721E_CLK_PARENT_48000];
priv->pll_rates[J721E_CLK_PARENT_48000] = clk_get_rate(pll);
!priv->pll_rates[J721E_CLK_PARENT_48000]) {
pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];
if (priv->pll_rates[J721E_CLK_PARENT_48000])
pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];