J721E_CLK_PARENT_44100
else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_44100])
clk_id = J721E_CLK_PARENT_44100;
clocks->parent[J721E_CLK_PARENT_44100] = parent;
if (!clocks->parent[J721E_CLK_PARENT_44100] &&
[J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */
[J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */
pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_44100]);
priv->pll_rates[J721E_CLK_PARENT_44100] =
match_data->pll_rates[J721E_CLK_PARENT_44100];
priv->pll_rates[J721E_CLK_PARENT_44100] = clk_get_rate(pll);
if (!priv->pll_rates[J721E_CLK_PARENT_44100] &&
if (priv->pll_rates[J721E_CLK_PARENT_44100])
pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];
pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];