IntrRxDone
if (intr_status & (IntrRxDone | IntrRxEmpty)) {
enable &= ~(IntrRxDone | IntrRxEmpty);
if (enable & (IntrRxDone | IntrRxEmpty)) {
enable &= ~(IntrRxDone | IntrRxEmpty);
writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
} while (intr_status & (IntrRxDone | IntrRxEmpty));
intr_status |= IntrRxDone | IntrRxEmpty;
writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
(IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
if (intr_status & IntrRxDone)
if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone)) &&
if (intr_status & (IntrRxDone | IntrEarlyRx)) {
IntrNormalSummary = IntrRxDone | IntrTxDone,
#define RHINE_EVENT_NAPI_RX (IntrRxDone | \