IntrEnable
enable = readl(ioaddr + IntrEnable);
writel(enable, ioaddr + IntrEnable);
readl(ioaddr + IntrEnable);
enable = readl(ioaddr + IntrEnable);
writel(enable, ioaddr + IntrEnable);
intr_status = readl(ioaddr + IntrEnable);
writel(intr_status, ioaddr + IntrEnable);
writel(0, ioaddr + IntrEnable);
ioaddr + IntrEnable);
iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
iowrite32(0x1A0F5, ioaddr + IntrEnable);
iowrite32(0x0000, ioaddr + IntrEnable);
iowrite32(0, ioaddr + IntrEnable);
BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
iowrite32(0x1A0F5, ioaddr + IntrEnable);
iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
ioaddr + IntrEnable);
iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
iowrite16(0x0000, ioaddr + IntrEnable);
iowrite16(0, ioaddr + IntrEnable);
iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
dev->name, ioread16(ioaddr + IntrEnable),
iowrite16(0, ioaddr + IntrEnable);
if (np->hands_off || !readl(ioaddr + IntrEnable))
writel(1, ns_ioaddr(dev) + IntrEnable);
readl(ns_ioaddr(dev) + IntrEnable);
writel(0, ns_ioaddr(dev) + IntrEnable);
readl(ns_ioaddr(dev) + IntrEnable);
iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);
iowrite16(0x0000, rp->base + IntrEnable);
iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable);
RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
iowrite16(enable_mask, ioaddr + IntrEnable);