IXGBE_RXDCTL
reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
{IXGBE_RXDCTL(0), "RXDCTL"},
vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
case IXGBE_RXDCTL(0):
regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));