IWL_DEBUG_ISR
IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
IWL_DEBUG_ISR(trans, "Enabling %s interrupt only\n",
IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n",
IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret,
IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry);
IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
IWL_DEBUG_ISR(trans, "IPC state = 0x%x/%d\n", val, state);
IWL_DEBUG_ISR(trans, "Reset flow completed\n");
IWL_DEBUG_ISR(trans, "TOP Reset continues\n");
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans, "Alive interrupt\n");
IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
IWL_DEBUG_ISR(trans, "Rx interrupt\n");
IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n");
IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans, "Alive interrupt\n");
IWL_DEBUG_ISR(trans,
IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");