ISPREG
#define IOBASE(vha) IOBAR(ISPREG(vha))
qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
qla27xx_read_reg(ISPREG(vha), offset, buf, len);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
qla24xx_pause_risc(ISPREG(vha), vha->hw);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
qla27xx_write_reg(ISPREG(vha), IOBASE_ADDR, 0x40, buf);
qla27xx_write_reg(ISPREG(vha), 0xc0, addr|0x80000000, buf);
qla27xx_read_reg(ISPREG(vha), 0xc4, buf, len);
qla27xx_write_reg(ISPREG(vha), IOBASE(vha), 0x40, buf);
qla27xx_write_reg(ISPREG(vha), 0xc4, data, buf);
qla27xx_write_reg(ISPREG(vha), 0xc0, addr, buf);
qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
qla27xx_read_reg(ISPREG(vha), data_addr, buf, len);
qla27xx_write_reg(ISPREG(vha), data_addr, wr_data, buf);
qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);