ISR
unsigned long pend = ISR;
AREG(EOI), AREG(RRR), AREG(LDR), AREG(DFR), AREG(SPIV), AREG(ISR), \
isr = error_data[ISR];
u16 ISR;
u32 status = at91_adc_readl(st, ISR);
.ISR = 0x30,
.ISR = 0x30,
*status = at91_adc_readl(st, ISR);
ack_isr = isr = saa7146_read(dev, ISR);
saa7146_write(dev, ISR, ack_isr);
isr = readl_relaxed(ctrl->regs + ISR);
writel_relaxed(isr, ctrl->regs + ISR);
isr = readl_relaxed(ctrl->regs + ISR);
writel_relaxed(isr, ctrl->regs + ISR);
unsigned int ISR;
queue_writel(queue, ISR, MACB_BIT(RCOMP));
queue_writel(queue, ISR, MACB_BIT(TCOMP));
status = queue_readl(queue, ISR);
queue_writel(queue, ISR, MACB_BIT(WOL));
status = queue_readl(queue, ISR);
queue_writel(queue, ISR, GEM_BIT(WOL));
status = queue_readl(queue, ISR);
queue_writel(queue, ISR, -1);
queue_writel(queue, ISR, MACB_BIT(RCOMP));
queue_writel(queue, ISR, MACB_BIT(TCOMP) |
queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
queue_writel(queue, ISR, MACB_BIT(RXUBR));
queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
queue_writel(queue, ISR, MACB_BIT(HRESP));
status = queue_readl(queue, ISR);
queue_readl(queue, ISR);
queue_writel(queue, ISR, -1);
queue->ISR = GEM_ISR(hw_q - 1);
queue->ISR = MACB_ISR;
intstatus = macb_readl(lp, ISR);
queue_readl(queue, ISR);
queue_writel(queue, ISR, -1);
queue_readl(bp->queues, ISR);
queue_writel(bp->queues, ISR, -1);
"config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
dev->name, ioread32(ioaddr + ISR));
u32 intr_status = ioread32(ioaddr + ISR);
iowrite32(intr_status, ioaddr + ISR);
dev->name, ioread32(ioaddr + ISR));
iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
isr = readl(dev->base + ISR);
isr = readl(dev->base + ISR);
BYTE_REG_BITS_OFF(ISR_PWEI, ®s->ISR);
#define mac_read_isr(regs) readl(&((regs)->ISR))
#define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
#define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
volatile __le32 ISR; /* 0x24 */
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
intvec->intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
rtl_write_dword(rtlpriv, ISR + 4, intvec->intb);
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
rtl_write_dword(rtlpriv, ISR, intvec->inta);
saa7146_write(x, ISR, (y));
err = vx_inb(chip, ISR);
if (vx_inb(chip, ISR) & ISR_ERR) {
if (vx_inb(chip, ISR) & ISR_ERR) {
status = atiixp_read(chip, ISR);
atiixp_write(chip, ISR, status);
atiixp_write(chip, ISR, 0xffffffff);
atiixp_write(chip, ISR, atiixp_read(chip, ISR));
atiixp_write(chip, ISR, status);
atiixp_write(chip, ISR, 0xffffffff);
atiixp_write(chip, ISR, atiixp_read(chip, ISR));
status = atiixp_read(chip, ISR);
isr = READREG(ISR);
WRITEREG(isr, ISR);
vx_inl(chip, ISR);
vx_inl(chip, ISR);
vx_inl(chip, ISR);
vx_inl(chip, ISR);
vx_inb(chip, ISR);
vx_outb(chip, ISR, 0);
isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
isr[i] = readl(kmb_i2s->i2s_base + ISR(i));