IR_DEC_REG1
regmap_read(ir->reg, IR_DEC_REG1, &duration);
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
.max_register = IR_DEC_REG1,