IRO
(IRO[107].base + ((funcId) * IRO[107].m1))
(IRO[279].base + ((pfId) * IRO[279].m1))
(IRO[280].base + ((pfId) * IRO[280].m1))
(IRO[281].base + ((pfId) * IRO[281].m1))
(IRO[282].base + ((pfId) * IRO[282].m1))
(IRO[278].base + ((pfId) * IRO[278].m1))
(IRO[277].base + ((pfId) * IRO[277].m1))
(IRO[276].base + ((pfId) * IRO[276].m1))
(IRO[275].base + ((pfId) * IRO[275].m1))
(IRO[285].base + ((pfId) * IRO[285].m1))
(IRO[271].base + ((pfId) * IRO[271].m1))
(IRO[272].base + ((pfId) * IRO[272].m1))
(IRO[273].base + ((pfId) * IRO[273].m1))
(IRO[274].base + ((pfId) * IRO[274].m1))
(IRO[206].base + ((pfId) * IRO[206].m1))
(IRO[109].base + ((funcId) * IRO[109].m1))
(IRO[224].base + ((pfId) * IRO[224].m1))
(IRO[108].base + ((funcId) * IRO[108].m1))
#define USTORM_AGG_DATA_OFFSET (IRO[213].base)
#define USTORM_AGG_DATA_SIZE (IRO[213].size)
#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
(IRO[180].base + ((assertListEntry) * IRO[180].m1))
(IRO[187].base + ((portId) * IRO[187].m1))
(IRO[326].base + ((pfId) * IRO[326].m1))
(IRO[182].base + ((funcId) * IRO[182].m1))
(IRO[290].base + ((pfId) * IRO[290].m1))
(IRO[291].base + ((pfId) * IRO[291].m1))
#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
(IRO[295].base + ((pfId) * IRO[295].m1))
(IRO[292].base + ((pfId) * IRO[292].m1))
(IRO[288].base + ((pfId) * IRO[288].m1))
(IRO[287].base + ((pfId) * IRO[287].m1))
(IRO[286].base + ((pfId) * IRO[286].m1))
(IRO[289].base + ((pfId) * IRO[289].m1))
(IRO[293].base + ((pfId) * IRO[293].m1))
(IRO[294].base + ((pfId) * IRO[294].m1))
(IRO[186].base + ((pfId) * IRO[186].m1))
(IRO[184].base + ((funcId) * IRO[184].m1))
(IRO[151].base + ((assertListEntry) * IRO[151].m1))
(IRO[216].base + ((portId) * IRO[216].m1) + ((clientId) * \
IRO[216].m2))
(IRO[217].base + ((qzoneId) * IRO[217].m1))
#define USTORM_TPA_BTR_OFFSET (IRO[214].base)
#define USTORM_TPA_BTR_SIZE (IRO[214].size)
(IRO[183].base + ((funcId) * IRO[183].m1))
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
(IRO[50].base + ((assertListEntry) * IRO[50].m1))
(IRO[43].base + ((portId) * IRO[43].m1))
(IRO[45].base + ((pfId) * IRO[45].m1))
(IRO[47].base + ((funcId) * IRO[47].m1))
(IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
(IRO[303].base + ((pfId) * IRO[303].m1))
(IRO[306].base + ((pfId) * IRO[306].m1))
(IRO[307].base + ((pfId) * IRO[307].m1))
(IRO[308].base + ((pfId) * IRO[308].m1))
(IRO[309].base + ((pfId) * IRO[309].m1))
IRO[157].m2))
(IRO[310].base + ((pfId) * IRO[310].m1))
(IRO[311].base + ((pfId) * IRO[311].m1))
(IRO[312].base + ((pfId) * IRO[312].m1))
(IRO[302].base + ((pfId) * IRO[302].m1))
(IRO[301].base + ((pfId) * IRO[301].m1))
(IRO[300].base + ((pfId) * IRO[300].m1))
(IRO[305].base + ((pfId) * IRO[305].m1))
(IRO[304].base + ((pfId) * IRO[304].m1))
(IRO[299].base + ((pfId) * IRO[299].m1))
(IRO[298].base + ((pfId) * IRO[298].m1))
(IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
(IRO[297].base + ((pfId) * IRO[297].m1))
(IRO[296].base + ((pfId) * IRO[296].m1))
(IRO[44].base + ((pfId) * IRO[44].m1))
(IRO[49].base + ((funcId) * IRO[49].m1))
(IRO[32].base + ((funcId) * IRO[32].m1))
IRO[158].m2))
#define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
(IRO[30].base + ((funcId) * IRO[30].m1))
(IRO[31].base + ((funcId) * IRO[31].m1))
(IRO[218].base + ((portId) * IRO[218].m1))
(IRO[219].base + ((portId) * IRO[219].m1))
(IRO[221].base + (((pfId)>>1) * IRO[221].m1) + (((pfId)&1) * \
IRO[221].m2))
(IRO[48].base + ((funcId) * IRO[48].m1))
(IRO[386].base + ((fid) * IRO[386].m1))
(IRO[163].base + ((funcId) * IRO[163].m1))
(IRO[153].base + ((funcId) * IRO[153].m1))
(IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
(IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
* IRO[142].m2) + ((sbId) * IRO[142].m3))
#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
(IRO[324].base + ((pfId) * IRO[324].m1))
(IRO[325].base + ((pfId) * IRO[325].m1))
(IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
(IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
(IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
(IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
(IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
(IRO[322].base + ((pfId) * IRO[322].m1) + ((iscsiEqId) * IRO[322].m2))
(IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
(IRO[323].base + ((pfId) * IRO[323].m1))
(IRO[315].base + ((pfId) * IRO[315].m1))
(IRO[314].base + ((pfId) * IRO[314].m1))
(IRO[313].base + ((pfId) * IRO[313].m1))
(IRO[155].base + ((funcId) * IRO[155].m1))
(IRO[146].base + ((pfId) * IRO[146].m1))
(IRO[147].base + ((pfId) * IRO[147].m1))
(IRO[145].base + ((pfId) * IRO[145].m1))
#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
(IRO[148].base + ((pfId) * IRO[148].m1))
#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
(IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
(IRO[137].base + ((sbId) * IRO[137].m1))
(IRO[138].base + ((sbId) * IRO[138].m1))
(IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
(IRO[136].base + ((sbId) * IRO[136].m1))
#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
(IRO[141].base + ((sbId) * IRO[141].m1))
#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
(IRO[159].base + ((vfId) * IRO[159].m1))
(IRO[160].base + ((vfId) * IRO[160].m1))
(IRO[154].base + ((funcId) * IRO[154].m1))
(IRO[207].base + ((pfId) * IRO[207].m1))
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
(IRO[205].base + ((pfId) * IRO[205].m1))
(IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base \
+ ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))
(IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)
(IRO[IRO_ETH_RX_RATE_LIMIT].base \
+ ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[IRO_ETH_RX_RATE_LIMIT].size)
(IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].base \
+ ((queue_id) * IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].m1))
#define MSTORM_ETH_PF_PRODS_GTT_SIZE (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].size)
(IRO[IRO_MSTORM_ETH_PF_STAT].base \
+ ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))
#define MSTORM_ETH_PF_STAT_SIZE (IRO[IRO_MSTORM_ETH_PF_STAT].size)
(IRO[IRO_MSTORM_ETH_VF_PRODS].base \
+ ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \
+ ((vf_queue_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m2))
#define MSTORM_ETH_VF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_VF_PRODS].size)
#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_MSTORM_INTEG_TEST_DATA].base)
#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_MSTORM_INTEG_TEST_DATA].size)
(IRO[IRO_MSTORM_ISCSI_RX_STATS].base \
+ ((storage_func_id) * IRO[IRO_MSTORM_ISCSI_RX_STATS].m1))
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_MSTORM_ISCSI_RX_STATS].size)
#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].base)
#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].size)
(IRO[IRO_MSTORM_QUEUE_STAT].base \
+ ((stat_counter_id) * IRO[IRO_MSTORM_QUEUE_STAT].m1))
#define MSTORM_QUEUE_STAT_SIZ (IRO[IRO_MSTORM_QUEUE_STAT].size)
(IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].m1))
#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].size)
(IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].base \
+ ((storage_func_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
+ ((bdq_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
(IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[IRO_MSTORM_TPA_TIMEOUT_US].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[IRO_MSTORM_TPA_TIMEOUT_US].size)
(IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].base \
+ ((ethtype_id) * IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].m1))
(IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].size)
(IRO[IRO_PSTORM_ETH_PF_STAT].base \
+ ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))
#define PSTORM_ETH_PF_STAT_SIZE (IRO[IRO_PSTORM_ETH_PF_STAT].size)
(IRO[IRO_PSTORM_FCOE_TX_STATS].base \
+ ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))
#define PSTORM_FCOE_TX_STATS_SIZE (IRO[IRO_PSTORM_FCOE_TX_STATS].size)
#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_PSTORM_INTEG_TEST_DATA].base)
#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_PSTORM_INTEG_TEST_DATA].size)
(IRO[IRO_PSTORM_ISCSI_TX_STATS].base \
+ ((storage_func_id) * IRO[IRO_PSTORM_ISCSI_TX_STATS].m1))
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_PSTORM_ISCSI_TX_STATS].size)
#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].base)
#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].size)
(IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].base \
+ ((pf_id) * IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].m1))
(IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].size)
(IRO[IRO_PSTORM_QUEUE_STAT].base \
+ ((stat_counter_id) * IRO[IRO_PSTORM_QUEUE_STAT].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_QUEUE_STAT].size)
(IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].m1))
#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].size)
(IRO[IRO_PSTORM_RDMA_QUEUE_STAT].base \
+ ((rdma_stat_counter_id) * IRO[IRO_PSTORM_RDMA_QUEUE_STAT].m1))
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].size)
(IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].base \
+ ((roce_pf_id) * IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].m1))
(IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].size)
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[IRO_TSTORM_ETH_PRS_INPUT].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[IRO_TSTORM_ETH_PRS_INPUT].size)
(IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].base \
+ ((pf_id) * IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].m1))
(IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].size)
(IRO[IRO_TSTORM_FCOE_RX_STATS].base \
+ ((pf_id) * IRO[IRO_TSTORM_FCOE_RX_STATS].m1))
#define TSTORM_FCOE_RX_STATS_SIZE (IRO[IRO_TSTORM_FCOE_RX_STATS].size)
#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_TSTORM_INTEG_TEST_DATA].base)
#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_TSTORM_INTEG_TEST_DATA].size)
(IRO[IRO_TSTORM_ISCSI_RX_STATS].base \
+ ((storage_func_id) * IRO[IRO_TSTORM_ISCSI_RX_STATS].m1))
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_TSTORM_ISCSI_RX_STATS].size)
(IRO[IRO_TSTORM_LL2_PORT_STAT].base \
+ ((port_id) * IRO[IRO_TSTORM_LL2_PORT_STAT].m1))
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[IRO_TSTORM_LL2_PORT_STAT].size)
(IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].base \
+ ((core_rx_queue_id) * IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].m1))
#define TSTORM_LL2_RX_PRODS_GTT_SIZE (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].size)
#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].base)
#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].size)
(IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].base \
+ ((pf_id) * IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].m1))
(IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].size)
(IRO[IRO_TSTORM_PORT_STAT].base \
+ ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))
#define TSTORM_PORT_STAT_SIZE (IRO[IRO_TSTORM_PORT_STAT].size)
(IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].m1))
#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].size)
(IRO[IRO_TSTORM_RDMA_QUEUE_STAT].base \
+ ((rdma_stat_counter_id) * IRO[IRO_TSTORM_RDMA_QUEUE_STAT].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].size)
(IRO[IRO_TSTORM_ROCE_EVENTS_STAT].base \
+ ((roce_pf_id) * IRO[IRO_TSTORM_ROCE_EVENTS_STAT].m1))
#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].size)
(IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].base \
+ ((storage_func_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
+ ((bdq_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
(IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
(IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].base \
+ ((cmdq_queue_id) * IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].m1))
(IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].size)
(IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].base \
+ ((queue_zone_id) * IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].m1))
(IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].size)
(IRO[IRO_USTORM_EQE_CONS_GTT].base \
+ ((pf_id) * IRO[IRO_USTORM_EQE_CONS_GTT].m1))
#define USTORM_EQE_CONS_GTT_SIZE (IRO[IRO_USTORM_EQE_CONS_GTT].size)
(IRO[IRO_USTORM_ETH_PF_STAT].base \
+ ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))
#define USTORM_ETH_PF_STAT_SIZE (IRO[IRO_USTORM_ETH_PF_STAT].size)
(IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].base \
+ ((queue_zone_id) * IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].m1))
#define USTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].size)
(IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].base \
+ ((pf_id) * IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].m1))
#define USTORM_FLR_FINAL_ACK_GTT_SIZE (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].size)
#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_USTORM_INTEG_TEST_DATA].base)
#define USTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_USTORM_INTEG_TEST_DATA].size)
(IRO[IRO_USTORM_ISCSI_RX_STATS].base \
+ ((storage_func_id) * IRO[IRO_USTORM_ISCSI_RX_STATS].m1))
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_USTORM_ISCSI_RX_STATS].size)
#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].base)
#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].size)
(IRO[IRO_USTORM_QUEUE_STAT].base \
+ ((stat_counter_id) * IRO[IRO_USTORM_QUEUE_STAT].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[IRO_USTORM_QUEUE_STAT].size)
(IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].m1))
#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].size)
(IRO[IRO_USTORM_ROCE_CQE_STATS].base \
+ ((roce_pf_id) * IRO[IRO_USTORM_ROCE_CQE_STATS].m1))
#define USTORM_ROCE_CQE_STATS_SIZE (IRO[IRO_USTORM_ROCE_CQE_STATS].size)
(IRO[IRO_USTORM_TOE_CQ_PROD].base \
+ ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))
#define USTORM_TOE_CQ_PROD_SIZE (IRO[IRO_USTORM_TOE_CQ_PROD].size)
(IRO[IRO_USTORM_TOE_GRQ_PROD].base \
+ ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))
#define USTORM_TOE_GRQ_PROD_SIZE (IRO[IRO_USTORM_TOE_GRQ_PROD].size)
(IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].base \
+ ((vf_id) * IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].m1))
(IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].size)
(IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].base \
+ ((queue_id) * IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].m1))
#define XSTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].size)
#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_XSTORM_INTEG_TEST_DATA].base)
#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_XSTORM_INTEG_TEST_DATA].size)
(IRO[IRO_XSTORM_ISCSI_TX_STATS].base \
+ ((storage_func_id) * IRO[IRO_XSTORM_ISCSI_TX_STATS].m1))
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_XSTORM_ISCSI_TX_STATS].size)
(IRO[IRO_XSTORM_IWARP_RXMIT_STATS].base \
+ ((pf_id) * IRO[IRO_XSTORM_IWARP_RXMIT_STATS].m1))
#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].size)
#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].base)
#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].size)
(IRO[IRO_XSTORM_PQ_INFO].base \
+ ((pq_id) * IRO[IRO_XSTORM_PQ_INFO].m1))
#define XSTORM_PQ_INFO_SIZE (IRO[IRO_XSTORM_PQ_INFO].size)
(IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].m1))
#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].size)
(IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].base)
(IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].size)
#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_YSTORM_INTEG_TEST_DATA].base)
#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_YSTORM_INTEG_TEST_DATA].size)
(IRO[IRO_YSTORM_ISCSI_TX_STATS].base \
+ ((storage_func_id) * IRO[IRO_YSTORM_ISCSI_TX_STATS].m1))
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_YSTORM_ISCSI_TX_STATS].size)
#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].base)
#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].size)
(IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].m1))
#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].size)
(IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].base \
+ ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].m1))
(IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].size)
(IRO[IRO_YSTORM_ROCE_ERROR_STATS].base \
+ ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_ERROR_STATS].m1))
#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[IRO_YSTORM_ROCE_ERROR_STATS].size)
(IRO[IRO_YSTORM_TOE_CQ_PROD].base \
+ ((rss_id) * IRO[IRO_YSTORM_TOE_CQ_PROD].m1))
#define YSTORM_TOE_CQ_PROD_SIZE (IRO[IRO_YSTORM_TOE_CQ_PROD].size)
(IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base \
+ ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))
(IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)
(IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base \
+ ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))
(IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)