IRQS_PER_BANK
if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
"bank %d irq %*pbl\n", b, IRQS_PER_BANK, ®);
for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
for_each_set_bit(n, &pending, IRQS_PER_BANK)
u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
domain = irq_domain_create_linear(of_fwnode_handle(node), drv_data->bank_nr * IRQS_PER_BANK,
ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
#define STM32MP_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp_exti_banks) * IRQS_PER_BANK)
u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
u32 val = BIT(d->hwirq % IRQS_PER_BANK);
val |= BIT(d->hwirq % IRQS_PER_BANK);
val &= ~BIT(d->hwirq % IRQS_PER_BANK);
u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
bank = hwirq / IRQS_PER_BANK;
if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) {
chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
for (i = 0; i < IRQS_PER_BANK; i++) {
event = bank * IRQS_PER_BANK + i;
domain = irq_domain_create_hierarchy(parent_domain, 0, drv_data->bank_nr * IRQS_PER_BANK,