arch/arm/mach-dove/bridge-regs.h

37

#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)

arch/arm/mach-dove/bridge-regs.h

38

#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)

arch/arm/mach-dove/bridge-regs.h

39

#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)

arch/arm/mach-dove/bridge-regs.h

40

#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)

arch/arm/mach-dove/bridge-regs.h

41

#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)

arch/arm/mach-dove/bridge-regs.h

42

#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)

arch/arm/mach-dove/bridge-regs.h

43

#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)

arch/arm/mach-dove/irq.c

40

static void __iomem *dove_irq_base = IRQ_VIRT_BASE;

arch/arm/mach-dove/irq.c

65

orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);

arch/arm/mach-dove/irq.c

66

orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);

arch/arm/mach-mv78xx0/irq.c

24

static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;

arch/arm/mach-mv78xx0/irq.c

56

orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);

arch/arm/mach-mv78xx0/irq.c

57

orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);

arch/arm/mach-mv78xx0/irq.c

58

orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);