arch/mips/ath79/clock.c

532

misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);

arch/mips/ath79/clock.c

534

ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);

drivers/irqchip/irq-ath79-misc.c

127

__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

44

__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

68

t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

69

__raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

72

__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

81

t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

82

__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);

drivers/irqchip/irq-ath79-misc.c

85

__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);