IRQ_INTERNAL_BASE
unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
do_IRQ(intbit + IRQ_INTERNAL_BASE);
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28)
#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14)
#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20)
#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21)
#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22)
#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25)
#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30)
#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27)
#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)
#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)
#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)
#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)
#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)