IRQENABLE_L1
[IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
od->context.irqenable_l1 = omap_dma_glbl_read(od, IRQENABLE_L1);
omap_dma_glbl_write(od, IRQENABLE_L1, od->context.irqenable_l1);
omap_dma_glbl_write(od, IRQENABLE_L1, 0);
omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);