IRQENABLE_L1

43

[IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },

1578

od->context.irqenable_l1 = omap_dma_glbl_read(od, IRQENABLE_L1);

1590

omap_dma_glbl_write(od, IRQENABLE_L1, od->context.irqenable_l1);

1778

omap_dma_glbl_write(od, IRQENABLE_L1, 0);

733

omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);

768

omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);