IR
writew(INT_STATUS, gpt_base + IR(CLKEVT));
int IR, cmp;
FP_CMP_S(IR, SA, SB, 3);
if (IR == 3 && (FP_ISSIGNAN_S(SA) || FP_ISSIGNAN_S(SB)))
if (IR == cmp) {
IR = 0x4;
IR = 0;
FP_CMP_D(IR, DA, DB, 3);
if (IR == 3 && (FP_ISSIGNAN_D(DA) || FP_ISSIGNAN_D(DB)))
if (IR == cmp) {
IR = 0x4;
IR = 0;
IR = (ch << 3) | (cl << 2) | ((ch | cl) << 1) |
regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
int IR;
case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
FP_CMP_S(IR, SB, SA, 3);
if (IR == 3 &&
FP_CMP_D(IR, DB, DA, 3);
if (IR == 3 &&
FP_CMP_Q(IR, QB, QA, 3);
if (IR == 3 &&
if (IR == -1) IR = 2;
fsr &= ~0xc00; fsr |= (IR << 10);
case 1: rd->s = IR; break;
int IR;
IR = 2;
IR = 0;
case 1: if (XR) IR = 1; break; /* Not Equal */
case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
case 4: if (XR == 1) IR = 1; break; /* Less */
case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
case 6: if (XR == 2) IR = 1; break; /* Greater */
case 7: if (XR == 3) IR = 1; break; /* Unordered */
IR ^= 1;
IR = 0;
case 1: if (XR & 4) IR = 1; break; /* Equal */
case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
case 3: if (freg) IR = 1; break; /* Less */
case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
case 5: if (XR & 1) IR = 1; break; /* Carry Set */
case 6: if (XR & 8) IR = 1; break; /* Negative */
case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
IR ^= 1;
IR = 0;
case 1: if (!XR) IR = 1; break; /* Register Zero */
case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
IR ^= 1;
if (IR == 0) {
} else if (IR == 1) {
case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
case 1: rd->s = IR; break;
MFIO_PIN_GROUP(72, IR),
TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0),
TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0),
TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, DPU0, DPU1, 0),
TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0),
TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0),
TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0),
SEC_PD(IR, 0),
uint32_t IR:1;
uint32_t IR:1;
__clear_bit(grp->index, &q->bitmaps[IR]);
__clear_bit(grp->index, &q->bitmaps[IR]);
qfq_move_groups(q, mask, IB, IR);
__clear_bit(grp->index, &q->bitmaps[IR]);
qfq_move_groups(q, mask, IB, IR);
qfq_move_groups(q, mask, IR, ER);
ineligible = q->bitmaps[IR] | q->bitmaps[IB];
azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR);
fsi_master_mask_set(master, SOFT_RST, IR, 0);
fsi_master_mask_set(master, SOFT_RST, IR, IR);