drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

16

#define IPC_REG_PISR_CHV_AB (IPC_REG_BASE + 0x00)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

18

#define IPC_REG_PIMR_CHV_AB (IPC_REG_BASE + 0x04)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

21

#define IPC_REG_PISR_BXT (IPC_REG_BASE + 0x0C)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

23

#define IPC_REG_PIMR_BXT (IPC_REG_BASE + 0x08)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

26

#define IPC_REG_ISH_HOST_FWSTS (IPC_REG_BASE + 0x34)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

28

#define IPC_REG_HOST_COMM (IPC_REG_BASE + 0x38)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

30

#define IPC_REG_ISH_RST (IPC_REG_BASE + 0x44)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

33

#define IPC_REG_HOST2ISH_DRBL (IPC_REG_BASE + 0x48)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

35

#define IPC_REG_ISH2HOST_DRBL (IPC_REG_BASE + 0x54)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

37

#define IPC_REG_ISH2HOST_MSG (IPC_REG_BASE + 0x60)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

39

#define IPC_REG_HOST2ISH_MSG (IPC_REG_BASE + 0xE0)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

41

#define IPC_REG_ISH_RMP2 (IPC_REG_BASE + 0x368)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

43

#define IPC_REG_MAX (IPC_REG_BASE + 0x400)