arch/mips/dec/setup.c

498

init_ioasic_irqs(IO_IRQ_BASE);

arch/mips/dec/setup.c

595

init_ioasic_irqs(IO_IRQ_BASE);

arch/mips/dec/setup.c

696

init_ioasic_irqs(IO_IRQ_BASE);

arch/mips/include/asm/dec/ioasic_ints.h

69

#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)

drivers/irqchip/irq-zevio.c

109

gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE;

drivers/irqchip/irq-zevio.c

110

gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE;

drivers/irqchip/irq-zevio.c

111

gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE;

drivers/irqchip/irq-zevio.c

112

gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET;

drivers/irqchip/irq-zevio.c

92

zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);