AR5K_SIMR2
REG_STRUCT_INIT(AR5K_SIMR2),
u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,