IP3_3_0
PINMUX_IPSR_GPSR(IP3_3_0, D14),
PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
PINMUX_IPSR_GPSR(IP3_3_0, A11),
PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
#define GPSR1_9 F_(A9, IP3_3_0)
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
IP3_3_0 ))
PINMUX_IPSR_GPSR(IP3_3_0, A9),
PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
#define GPSR1_9 F_(A9, IP3_3_0)
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
IP3_3_0 ))
PINMUX_IPSR_GPSR(IP3_3_0, A9),
PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
#define GPSR1_9 F_(A9, IP3_3_0)
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
IP3_3_0 ))
PINMUX_IPSR_GPSR(IP3_3_0, A9),
PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
IP3_3_0 ))
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
PINMUX_IPSR_GPSR(IP3_3_0, RX3),
PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
IP3_3_0 ))
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
PINMUX_IPSR_GPSR(IP3_3_0, RX3),
PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
#define GPSR1_1 F_(A1, IP3_3_0)
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
IP3_3_0 ))
PINMUX_IPSR_GPSR(IP3_3_0, A1),
PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
PINMUX_IPSR_GPSR(IP3_3_0, IETX),
PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
IP3_3_0 ))
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
#define GPSR1_17 F_(DU_DR1, IP3_3_0)