IP1_15_12
PINMUX_IPSR_GPSR(IP1_15_12, D1),
PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
#define GPSR2_5 F_(IRQ5, IP1_15_12)
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
IP1_15_12
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
#define GPSR2_5 F_(IRQ5, IP1_15_12)
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
IP1_15_12
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
#define GPSR2_5 F_(IRQ5, IP1_15_12)
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
IP1_15_12
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
IP1_15_12
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
PINMUX_IPSR_GPSR(IP1_15_12, A11),
PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
#define GPSR0_11 F_(DU_DG7, IP1_15_12)
IP1_15_12
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
PINMUX_IPSR_GPSR(IP1_15_12, A11),
#define GPSR0_11 F_(DU_DG7, IP1_15_12)
#define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
IP1_15_12
PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
IP1_15_12
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
#define GPSR1_4 F_(DU_DB4, IP1_15_12)