IP1SR1_31_28
#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
IP1SR1_31_28
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N),
PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N),
PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5),
PINMUX_IPSR_GPSR(IP1SR1_31_28, A15),
IP1SR1_31_28
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
#define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
#define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
IP1SR1_31_28
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),