IP1SR0_27_24
IP1SR0_27_24
FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP1SR0_27_24, HSCK3),
PINMUX_IPSR_GPSR(IP1SR0_27_24, SCK1),
#define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24)
IP1SR0_27_24
FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
IP1SR0_27_24
FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),