IP0SR2_31_28
#define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
IP0SR2_31_28
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3),
#define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)
IP0SR2_31_28
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
IP0SR2_31_28
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),