IP0SR1_15_12
#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
IP0SR1_15_12
FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
IP0SR1_15_12
FM(IP0SR1_15_12) IP0SR1_15_12 \
PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0),
PINMUX_IPSR_PHYS(IP0SR1_15_12, SDA1, SEL_I2C1_3),
#define GPSR1_3 F_(GP1_03, IP0SR1_15_12)
#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
IP0SR1_15_12
FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
IP0SR1_15_12
FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),