AR5K_REG_SM
AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210);
AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210) |
AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
AR5K_REG_SM(antenna_mode,
AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211);
AR5K_REG_SM(key_index,
txctl0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
txctl2 = AR5K_REG_SM(tx_tries0, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
txctl1 |= AR5K_REG_SM(key_index,
txctl3 |= AR5K_REG_SM(rtscts_rate,
AR5K_REG_SM(tx_tries##_n, \
AR5K_REG_SM(tx_rate##_n, \
AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR),
AR5K_REG_SM(ath5k_hw_reg_read(ah,
AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
AR5K_REG_SM(spur_delta_phase,
AR5K_REG_SM(spur_freq_sigma_delta,
AR5K_REG_SM(pd_gain_overlap,
AR5K_REG_SM(gain_boundaries[0],
AR5K_REG_SM(gain_boundaries[1],
AR5K_REG_SM(gain_boundaries[2],
AR5K_REG_SM(gain_boundaries[3],
reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
| AR5K_REG_SM(ah->ah_retry_long,
| AR5K_REG_SM(ah->ah_retry_short,
| AR5K_REG_SM(ah->ah_retry_long,
| AR5K_REG_SM(ah->ah_retry_short,
AR5K_REG_SM(ah->ah_retry_long,
| AR5K_REG_SM(ah->ah_retry_long,
| AR5K_REG_SM(max(ah->ah_retry_long, ah->ah_retry_short),
AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),
ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
AR5K_REG_SM(ah->ah_txq_imr_txdesc,
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
AR5K_REG_SM(ah->ah_txq_imr_txeol,
AR5K_REG_SM(ah->ah_txq_imr_txurn,
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
eifs_clock = AR5K_REG_SM(eifs_clock, AR5K_IFS1_EIFS);
pifs_clock = AR5K_REG_SM(pifs_clock, AR5K_IFS1_PIFS);
AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
usec = AR5K_REG_SM(usec, AR5K_USEC_1);
sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
txlat = AR5K_REG_SM(txlat * 2,
rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
txlat = AR5K_REG_SM(txlat * 4,
rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
rxlat = AR5K_REG_SM(rxlat / 2,
(AR5K_REG_SM(2,
AR5K_REG_SM(2,