AR5K_REG_MS
ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
ts->ts_final_retry = AR5K_REG_MS(tx_status->tx_status_0,
ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
ts->ts_tstamp = AR5K_REG_MS(txstat0,
ts->ts_shortretry = AR5K_REG_MS(txstat0,
ts->ts_final_retry = AR5K_REG_MS(txstat0,
ts->ts_seqnum = AR5K_REG_MS(txstat1,
ts->ts_rssi = AR5K_REG_MS(txstat1,
ts->ts_final_idx = AR5K_REG_MS(txstat1,
rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
rs->rs_rssi = AR5K_REG_MS(rxstat0,
rs->rs_rate = AR5K_REG_MS(rxstat0,
rs->rs_antenna = AR5K_REG_MS(rxstat0,
rs->rs_tstamp = AR5K_REG_MS(rxstat1,
rs->rs_keyix = AR5K_REG_MS(rxstat1,
rs->rs_phyerr = AR5K_REG_MS(rxstat1,
trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);