AR5K_PHY_IQ
{ AR5K_PHY_IQ, 0x00000000 },
{ AR5K_PHY_IQ, 0x05100000 },
else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) {
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
} else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);