AR5K_PHY_AGCCTL
v = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL);
{ AR5K_PHY_AGCCTL, 0x00001d08 },
{ AR5K_PHY_AGCCTL,
{ AR5K_PHY_AGCCTL,
if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,