AR5K_PHY_AGC
{ AR5K_PHY_AGC, 0x00000000 },
{ AR5K_PHY_AGC, 0x00000000 },
AR5K_PHY_AGC);
ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC);
{ AR5K_PHY_AGC, 0x00000000 },
{ AR5K_PHY_AGC, 0x00000000 },
{ AR5K_PHY_AGC, 0x00000000 },
{ AR5K_PHY_AGC, 0x00000000 },
{ AR5K_PHY_AGC, 0x00000000 },
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);