arch/x86/events/core.c

1261

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:

arch/x86/events/core.c

1263

hwc->event_base = x86_pmu_fixed_ctr_addr(idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/core.c

1264

hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |

arch/x86/events/core.c

2561

if (i >= INTEL_PMC_IDX_FIXED) {

arch/x86/events/core.c

2563

if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask)))

arch/x86/events/core.c

2566

wrmsrq(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0);

arch/x86/events/core.c

903

if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {

arch/x86/events/core.c

904

idx = INTEL_PMC_IDX_FIXED;

arch/x86/events/core.c

918

for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

3025

mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);

arch/x86/events/intel/core.c

3034

if (idx < INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

3039

x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);

arch/x86/events/intel/core.c

3073

case 0 ... INTEL_PMC_IDX_FIXED - 1:

arch/x86/events/intel/core.c

3078

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

arch/x86/events/intel/core.c

3392

idx -= INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/core.c

3410

if (idx < INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

3417

msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);

arch/x86/events/intel/core.c

3556

case 0 ... INTEL_PMC_IDX_FIXED - 1:

arch/x86/events/intel/core.c

3573

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

arch/x86/events/intel/core.c

5970

*intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/core.c

6013

if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

6179

#define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED))

arch/x86/events/intel/core.c

7637

c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/core.c

7716

if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))

arch/x86/events/intel/ds.c

1687

if (idx >= INTEL_PMC_IDX_FIXED)

arch/x86/events/intel/ds.c

1688

*pebs_data_cfg |= PEBS_DATACFG_FIX_BIT(idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

1866

if (hwc->idx >= INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/ds.c

1868

idx = hwc->idx - INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/ds.c

1927

if (idx >= INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/ds.c

1929

idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

1931

idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

2402

(bit + INTEL_PMC_IDX_FIXED == INTEL_PMC_IDX_FIXED_SLOTS)) {

arch/x86/events/intel/ds.c

2406

intel_perf_event_update_pmc(cpuc->events[bit + INTEL_PMC_IDX_FIXED],

arch/x86/events/intel/ds.c

3024

short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3025

short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3041

mask |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/ds.c

3042

size = INTEL_PMC_IDX_FIXED + x86_pmu_max_num_counters_fixed(NULL);

arch/x86/events/intel/ds.c

3187

short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3188

void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];

arch/x86/events/intel/ds.c

3206

(hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

3238

short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3239

void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];

arch/x86/events/perf_event.h

1462

return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));

arch/x86/events/zhaoxin/core.c

293

int idx = hwc->idx - INTEL_PMC_IDX_FIXED;

arch/x86/events/zhaoxin/core.c

317

int idx = hwc->idx - INTEL_PMC_IDX_FIXED;

arch/x86/events/zhaoxin/core.c

609

x86_pmu.intel_ctrl |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED;

arch/x86/include/asm/perf_event.h

344

#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)

arch/x86/include/asm/perf_event.h

348

#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)

arch/x86/include/asm/perf_event.h

352

#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)

arch/x86/include/asm/perf_event.h

357

#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)

arch/x86/include/asm/perf_event.h

376

#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)

arch/x86/include/asm/perf_event.h

384

#define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)

arch/x86/kvm/pmu.h

24

#define KVM_FIXED_PMC_BASE_IDX INTEL_PMC_IDX_FIXED