drivers/gpu/drm/i915/display/intel_lt_phy.c

1275

val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1800

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1806

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1809

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1814

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1871

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1875

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1880

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1884

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2009

rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2144

u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;

drivers/gpu/drm/i915/display/intel_lt_phy.c

2247

lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;

drivers/gpu/drm/i915/display/intel_lt_phy.c

2250

pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

2253

pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2259

intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

33

INTEL_LT_PHY_LANE0)

drivers/gpu/drm/i915/display/intel_lt_phy.c

969

? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;