drivers/gpu/drm/i915/display/intel_cx0_phy.c

2241

u8 lane = INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2255

cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2286

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2290

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2291

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2298

intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2573

serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2576

vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2581

vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2711

cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2721

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2725

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2733

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2737

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2746

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2750

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2758

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2762

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2834

cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2844

intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2852

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2856

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2864

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2868

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2877

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2881

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2888

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2892

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3058

u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3132

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3176

INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3452

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

35

#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3533

u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

518

u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

76

? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;