INTR_ENABLE
out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
writeb(INTR_ENABLE, tms_priv->mmiobase + HPREG_CCR);
writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE);
cdns_ctrl->reg + INTR_ENABLE);
jwrite32f(jme, JME_IENC, INTR_ENABLE);
jwrite32f(jme, JME_IENS, INTR_ENABLE);
if (unlikely((intrstat & INTR_ENABLE) == 0))
jwrite32(jme, JME_IENS, INTR_ENABLE);
jwrite32f(jme, JME_IENC, INTR_ENABLE);
static const u32 INTR_ENABLE = INTR_SWINTR |
writel_relaxed(MSI_CTRL_INT, k1->link + INTR_ENABLE);
writel_relaxed(0, k1->link + INTR_ENABLE);
mbox_cmd[1] = INTR_ENABLE;