arch/x86/events/core.c

1251

case INTEL_PMC_IDX_FIXED_BTS:

arch/x86/events/core.c

1261

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:

arch/x86/events/intel/bts.c

543

if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))

arch/x86/events/intel/core.c

2514

if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))

arch/x86/events/intel/core.c

2540

if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {

arch/x86/events/intel/core.c

2542

cpuc->events[INTEL_PMC_IDX_FIXED_BTS];

arch/x86/events/intel/core.c

2826

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

arch/x86/events/intel/core.c

2832

case INTEL_PMC_IDX_FIXED_BTS:

arch/x86/events/intel/core.c

3311

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

arch/x86/events/intel/core.c

3318

case INTEL_PMC_IDX_FIXED_BTS:

arch/x86/events/intel/ds.c

1116

EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);

arch/x86/events/intel/ds.c

1164

struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];