arch/x86/events/core.c

1261

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:

arch/x86/events/core.c

1263

hwc->event_base = x86_pmu_fixed_ctr_addr(idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/core.c

1264

hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |

arch/x86/events/core.c

2558

if (i >= INTEL_PMC_IDX_FIXED) {

arch/x86/events/core.c

2560

if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask)))

arch/x86/events/core.c

2563

wrmsrq(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0);

arch/x86/events/core.c

903

if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {

arch/x86/events/core.c

904

idx = INTEL_PMC_IDX_FIXED;

arch/x86/events/core.c

918

for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

2773

mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);

arch/x86/events/intel/core.c

2782

if (idx < INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

2787

x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);

arch/x86/events/intel/core.c

2821

case 0 ... INTEL_PMC_IDX_FIXED - 1:

arch/x86/events/intel/core.c

2826

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

arch/x86/events/intel/core.c

3140

idx -= INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/core.c

3158

if (idx < INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

3165

msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);

arch/x86/events/intel/core.c

3303

case 0 ... INTEL_PMC_IDX_FIXED - 1:

arch/x86/events/intel/core.c

3311

case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

arch/x86/events/intel/core.c

5690

*intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/core.c

5733

if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/core.c

5893

#define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED))

arch/x86/events/intel/core.c

7351

c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/core.c

7430

if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))

arch/x86/events/intel/ds.c

1679

if (idx >= INTEL_PMC_IDX_FIXED)

arch/x86/events/intel/ds.c

1680

*pebs_data_cfg |= PEBS_DATACFG_FIX_BIT(idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

1858

if (hwc->idx >= INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/ds.c

1860

idx = hwc->idx - INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/ds.c

1919

if (idx >= INTEL_PMC_IDX_FIXED) {

arch/x86/events/intel/ds.c

1921

idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

1923

idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

2394

(bit + INTEL_PMC_IDX_FIXED == INTEL_PMC_IDX_FIXED_SLOTS)) {

arch/x86/events/intel/ds.c

2398

intel_perf_event_update_pmc(cpuc->events[bit + INTEL_PMC_IDX_FIXED],

arch/x86/events/intel/ds.c

3016

short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3017

short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3033

mask |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED;

arch/x86/events/intel/ds.c

3034

size = INTEL_PMC_IDX_FIXED + x86_pmu_max_num_counters_fixed(NULL);

arch/x86/events/intel/ds.c

3179

short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3180

void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];

arch/x86/events/intel/ds.c

3198

(hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

3230

short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};

arch/x86/events/intel/ds.c

3231

void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];

arch/x86/events/perf_event.h

1454

return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));

arch/x86/events/zhaoxin/core.c

292

int idx = hwc->idx - INTEL_PMC_IDX_FIXED;

arch/x86/events/zhaoxin/core.c

316

int idx = hwc->idx - INTEL_PMC_IDX_FIXED;

arch/x86/events/zhaoxin/core.c

608

x86_pmu.intel_ctrl |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED;

arch/x86/include/asm/perf_event.h

342

#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)

arch/x86/include/asm/perf_event.h

346

#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)

arch/x86/include/asm/perf_event.h

350

#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)

arch/x86/include/asm/perf_event.h

355

#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)

arch/x86/include/asm/perf_event.h

374

#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)

arch/x86/include/asm/perf_event.h

382

#define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)

arch/x86/kvm/pmu.h

24

#define KVM_FIXED_PMC_BASE_IDX INTEL_PMC_IDX_FIXED