drivers/gpu/drm/i915/display/intel_lt_phy.c

1021

? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1310

val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1824

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1830

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1833

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1838

intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1895

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1899

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1904

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),

drivers/gpu/drm/i915/display/intel_lt_phy.c

1908

intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),

drivers/gpu/drm/i915/display/intel_lt_phy.c

2031

rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2166

u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;

drivers/gpu/drm/i915/display/intel_lt_phy.c

2243

lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;

drivers/gpu/drm/i915/display/intel_lt_phy.c

2247

pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2253

intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,

drivers/gpu/drm/i915/display/intel_lt_phy.c

32

INTEL_LT_PHY_LANE0)