drivers/gpu/drm/i915/display/intel_cx0_phy.c

2228

u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2254

u8 lane = INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2300

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2304

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2305

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2312

intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2589

serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2592

vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2597

vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2780

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2784

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2792

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2796

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2805

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2809

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2817

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2821

INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2895

cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2905

intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2913

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2917

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2925

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2929

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2938

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2942

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2949

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2953

intel_c20_sram_write(encoder, INTEL_CX0_LANE0,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3113

u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3187

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3232

INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

34

#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3502

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3583

u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

513

u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

75

? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;