INTEL_CX0_BOTH_LANES
intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES);
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||
return INTEL_CX0_BOTH_LANES;
? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)