drivers/gpu/drm/i915/display/i9xx_wm.c

195

was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

198

intel_de_write(display, INSTPM, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

199

intel_de_posting_read(display, INSTPM);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

102

sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/gt/intel_workarounds.c

339

wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);

drivers/gpu/drm/i915/gt/intel_workarounds.c

348

wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);

drivers/gpu/drm/i915/gt/intel_workarounds.c

365

wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);

drivers/gpu/drm/i915/gvt/cmd_parser.c

933

offset == i915_mmio_reg_offset(INSTPM)))

drivers/gpu/drm/i915/gvt/mmio_context.c

65

{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

97

{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

drivers/gpu/drm/i915/intel_clock_gating.c

673

intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));