IMX6SX_CLK_SSI1_PODF
hws[IMX6SX_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
clk_set_rate(hws[IMX6SX_CLK_SSI1_PODF]->clk, 24576000);