IMX296_REG_8BIT
#define IMX296_VINT IMX296_REG_8BIT(0x30aa)
#define IMX296_LOWLAGTRG IMX296_REG_8BIT(0x30ae)
#define IMX296_I2CCTRL IMX296_REG_8BIT(0x30ef)
#define IMX296_GAINCTRL IMX296_REG_8BIT(0x3200)
#define IMX296_GAINDLY IMX296_REG_8BIT(0x3212)
#define IMX296_PGCTRL IMX296_REG_8BIT(0x3238)
#define IMX296_PGHPSTEP IMX296_REG_8BIT(0x323e)
#define IMX296_PGVPSTEP IMX296_REG_8BIT(0x323f)
#define IMX296_PGHPNUM IMX296_REG_8BIT(0x3240)
#define IMX296_PGVPNUM IMX296_REG_8BIT(0x3241)
#define IMX296_PGHGSTEP IMX296_REG_8BIT(0x3249)
#define IMX296_FID0_ROI IMX296_REG_8BIT(0x3300)
#define IMX296_SST_SIEASTA1_SET IMX296_REG_8BIT(0x40c9)
#define IMX296_HSST IMX296_REG_8BIT(0x40dc)
#define IMX296_CKREQSEL IMX296_REG_8BIT(0x4101)
#define IMX296_GTTABLENUM IMX296_REG_8BIT(0x4114)
#define IMX296_CTRL418C IMX296_REG_8BIT(0x418c)
#define IMX296_CTRL00 IMX296_REG_8BIT(0x3000)
#define IMX296_CTRL08 IMX296_REG_8BIT(0x3008)
#define IMX296_CTRL0A IMX296_REG_8BIT(0x300a)
#define IMX296_CTRL0B IMX296_REG_8BIT(0x300b)
#define IMX296_CTRL0D IMX296_REG_8BIT(0x300d)
#define IMX296_CTRL0E IMX296_REG_8BIT(0x300e)
{ IMX296_REG_8BIT(0x3005), 0xf0 },
{ IMX296_REG_8BIT(0x309e), 0x04 },
{ IMX296_REG_8BIT(0x30a0), 0x04 },
{ IMX296_REG_8BIT(0x30a1), 0x3c },
{ IMX296_REG_8BIT(0x30a4), 0x5f },
{ IMX296_REG_8BIT(0x30a8), 0x91 },
{ IMX296_REG_8BIT(0x30ac), 0x28 },
{ IMX296_REG_8BIT(0x30af), 0x09 },
{ IMX296_REG_8BIT(0x30df), 0x00 },
{ IMX296_REG_8BIT(0x3165), 0x00 },
{ IMX296_REG_8BIT(0x3169), 0x10 },
{ IMX296_REG_8BIT(0x316a), 0x02 },
{ IMX296_REG_8BIT(0x31c8), 0xf3 }, /* Exposure-related */
{ IMX296_REG_8BIT(0x31d0), 0xf4 }, /* Exposure-related */
{ IMX296_REG_8BIT(0x321a), 0x00 },
{ IMX296_REG_8BIT(0x3226), 0x02 },
{ IMX296_REG_8BIT(0x3256), 0x01 },
{ IMX296_REG_8BIT(0x3541), 0x72 },
{ IMX296_REG_8BIT(0x3516), 0x77 },
{ IMX296_REG_8BIT(0x350b), 0x7f },
{ IMX296_REG_8BIT(0x3758), 0xa3 },
{ IMX296_REG_8BIT(0x3759), 0x00 },
{ IMX296_REG_8BIT(0x375a), 0x85 },
{ IMX296_REG_8BIT(0x375b), 0x00 },
{ IMX296_REG_8BIT(0x3832), 0xf5 },
{ IMX296_REG_8BIT(0x3833), 0x00 },
{ IMX296_REG_8BIT(0x38a2), 0xf6 },
{ IMX296_REG_8BIT(0x38a3), 0x00 },
{ IMX296_REG_8BIT(0x3a00), 0x80 },
{ IMX296_REG_8BIT(0x3d48), 0xa3 },
{ IMX296_REG_8BIT(0x3d49), 0x00 },
{ IMX296_REG_8BIT(0x3d4a), 0x85 },
{ IMX296_REG_8BIT(0x3d4b), 0x00 },
{ IMX296_REG_8BIT(0x400e), 0x58 },
{ IMX296_REG_8BIT(0x4014), 0x1c },
{ IMX296_REG_8BIT(0x4041), 0x2a },
#define IMX296_TMDCTRL IMX296_REG_8BIT(0x301d)
{ IMX296_REG_8BIT(0x40a2), 0x06 },
{ IMX296_REG_8BIT(0x40c1), 0xf6 },
{ IMX296_REG_8BIT(0x40c7), 0x0f },
{ IMX296_REG_8BIT(0x40c8), 0x00 },
{ IMX296_REG_8BIT(0x4174), 0x00 },
#define IMX296_WDSEL IMX296_REG_8BIT(0x3021)
#define IMX296_BLKLEVELAUTO IMX296_REG_8BIT(0x3022)
#define IMX296_SST IMX296_REG_8BIT(0x3024)
#define IMX296_CTRLTOUT IMX296_REG_8BIT(0x3026)
#define IMX296_CTRLTRIG IMX296_REG_8BIT(0x3029)
#define IMX296_SYNCSEL IMX296_REG_8BIT(0x3036)
#define IMX296_PULSE1 IMX296_REG_8BIT(0x306d)
#define IMX296_PULSE2 IMX296_REG_8BIT(0x3079)
#define IMX296_INCKSEL(n) IMX296_REG_8BIT(0x3089 + (n))
#define IMX296_VBLANKLP IMX296_REG_8BIT(0x309c)
#define IMX296_EXP_CNT IMX296_REG_8BIT(0x30a3)