arch/powerpc/xmon/ppc-opc.c

2880

#define APU_RT_MASK (APU_MASK | RT_MASK)

arch/powerpc/xmon/ppc-opc.c

2881

#define APU_RA_MASK (APU_MASK | RA_MASK)

arch/powerpc/xmon/ppc-opc.c

3522

{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3523

{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3552

{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3553

{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3592

{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3593

{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3608

{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3610

{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3634

{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3635

{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3661

{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3662

{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3693

{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3694

{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3716

{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3717

{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3750

{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3751

{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3758

{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3759

{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3766

{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3767

{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3774

{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3776

{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3783

{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3784

{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3795

{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3796

{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3805

{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3806

{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3815

{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

3817

{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},

arch/powerpc/xmon/ppc-opc.c

4696

{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4770

{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4834

{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4860

{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4898

{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4950

{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4982

{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5022

{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5074

{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5434

{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5759

{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5812

{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5835

{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5865

{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5883

{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5923

{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5942

{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5980

{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6020

{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6137

{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},