IMGU_REG_BASE
#define IMGU_REG_SP_ICACHE_ADDR(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x11c)
#define IMGU_REG_SP_CTRL_SINK(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x130)
#define IMGU_REG_SP_PC(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x134)
#define IMGU_REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300)
#define IMGU_REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
#define IMGU_REG_CIO_GATE_BURST_STATE (IMGU_REG_BASE + 0x404)
#define IMGU_REG_GP_BUSY (IMGU_REG_BASE + 0x500)
#define IMGU_REG_GP_STARVING (IMGU_REG_BASE + 0x504)
#define IMGU_REG_GP_WORKLOAD (IMGU_REG_BASE + 0x508)
#define IMGU_REG_GP_IRQ(n) (IMGU_REG_BASE + (n) * 4 + 0x50c) /* n = 0..4 */
#define IMGU_REG_GP_SP1_STRMON_STAT (IMGU_REG_BASE + 0x520)
#define IMGU_REG_GP_SP2_STRMON_STAT (IMGU_REG_BASE + 0x524)
#define IMGU_REG_GP_ISP_STRMON_STAT (IMGU_REG_BASE + 0x528)
#define IMGU_REG_GP_MOD_STRMON_STAT (IMGU_REG_BASE + 0x52c)
#define IMGU_REG_GP_HALT (IMGU_REG_BASE + 0x5dc)
#define IMGU_REG_IRQCTRL_BASE(n) (IMGU_REG_BASE + (n) * 0x100 + 0x700)
#define IMGU_REG_GP_TIMER (IMGU_REG_BASE + 0xa34)
#define IMGU_REG_SP_DMEM_BASE(n) (IMGU_REG_BASE + (n) * 0x4000 + 0x4000)
#define IMGU_REG_ISP_DMEM_BASE (IMGU_REG_BASE + 0xc000)
#define IMGU_REG_GDC_BASE (IMGU_REG_BASE + 0x18000)
#define IMGU_REG_ISP_CTRL (IMGU_REG_BASE + 0x00)
#define IMGU_REG_ISP_START_ADDR (IMGU_REG_BASE + 0x04)
#define IMGU_REG_ISP_ICACHE_ADDR (IMGU_REG_BASE + 0x10)
#define IMGU_REG_ISP_PC (IMGU_REG_BASE + 0x1c)
#define IMGU_REG_SP_CTRL(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x100)
#define IMGU_REG_SP_START_ADDR(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x104)
#define REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300)
#define REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
#define REG_GP_HALT (IMGU_REG_BASE + 0x5dc)
#define REG_GP_HALTED (IMGU_REG_BASE + 0x5e0)