IL49_SCD_START_OFFSET
#define IL49_SCD_SRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x0)
#define IL49_SCD_EMPTY_BITS (IL49_SCD_START_OFFSET + 0x4)
#define IL49_SCD_DRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x10)
#define IL49_SCD_TXFACT (IL49_SCD_START_OFFSET + 0x1c)
#define IL49_SCD_QUEUE_WRPTR(x) (IL49_SCD_START_OFFSET + 0x24 + (x) * 4)
#define IL49_SCD_QUEUE_RDPTR(x) (IL49_SCD_START_OFFSET + 0x64 + (x) * 4)
#define IL49_SCD_QUEUECHAIN_SEL (IL49_SCD_START_OFFSET + 0xd0)
#define IL49_SCD_INTERRUPT_MASK (IL49_SCD_START_OFFSET + 0xe4)
(IL49_SCD_START_OFFSET + 0x104 + (x) * 4)