IIR
iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));
xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);
assert_iir_is_zero(mmio, IIR(irqregs));
xe_mmio_write32(mmio, IIR(irqregs), ~0);
xe_mmio_read32(mmio, IIR(irqregs));
xe_mmio_write32(mmio, IIR(irqregs), ~0);
xe_mmio_read32(mmio, IIR(irqregs));
if ((iir = inb(IIR(dev->base_addr))) & 1)
iir = inb(IIR(dev->base_addr));
u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
if ((iir = inb(IIR(dev->base_addr))) & 1)
iir = inb(IIR(dev->base_addr));
u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) {
i810_readw(IIR, mmio),