drivers/gpu/drm/amd/amdgpu/cz_ih.c

130

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

132

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

135

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

222

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

228

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

84

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

130

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

132

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

135

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

221

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

227

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

84

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

143

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

152

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

163

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

168

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

219

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

221

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

223

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

225

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

229

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

231

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

232

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

233

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

280

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

282

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

283

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

466

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

472

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

191

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

193

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

195

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

197

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

201

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

203

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

205

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

252

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

254

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

255

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

434

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

440

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

191

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

193

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

195

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

197

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

201

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

203

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

205

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

252

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

254

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

255

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

459

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

465

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

162

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

163

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

166

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

217

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

219

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

221

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

223

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

227

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

229

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

230

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

231

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

278

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

280

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

442

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

448

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/si_ih.c

126

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

128

WREG32(IH_RB_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/si_ih.c

134

WREG32(IH_RB_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/si_ih.c

39

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

44

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/si_ih.c

50

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

55

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/si_ih.c

87

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

126

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

127

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

129

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

130

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

133

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

225

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

231

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

64

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

65

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

81

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

82

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

106

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

107

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

110

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

162

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

164

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

166

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

168

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

172

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

174

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

175

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

176

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

223

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

225

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

372

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

378

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

114

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

115

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

121

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

130

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

141

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

146

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

198

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

200

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

202

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

208

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

210

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

211

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

212

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

259

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

261

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

456

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

462

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/radeon/cik.c

6815

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/cik.c

6820

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/cik.c

6833

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/cik.c

6838

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/cik.c

6982

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/cik.c

7499

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/cik.c

7501

WREG32(IH_RB_CNTL, tmp);

drivers/gpu/drm/radeon/evergreen.c

4700

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/evergreen.c

4702

WREG32(IH_RB_CNTL, tmp);

drivers/gpu/drm/radeon/r600.c

3593

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

3598

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/r600.c

3604

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

3609

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/r600.c

3721

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/r600.c

4055

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

4057

WREG32(IH_RB_CNTL, tmp);

drivers/gpu/drm/radeon/si.c

5903

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/si.c

5908

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/si.c

5914

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/si.c

5919

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/si.c

6005

WREG32(IH_RB_CNTL, ih_rb_cntl);

drivers/gpu/drm/radeon/si.c

6208

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/si.c

6210

WREG32(IH_RB_CNTL, tmp);